Search
beautypg.com
Directory
Brands
Altera manuals
Measuring instruments
Santa Cruz
Manual
Altera Santa Cruz User Manual
Altera Measuring instruments
Text mode
Original mode
Altera Santa Cruz User Manual | 28 pages
Pages:
1
2
3
4
5
6
7
…
28
wrong Brand
wrong Model
non readable
This manual is related to the following products:
Santa USB
Santa MICTOR
Santa SD Card HSMC
Table of contents
Document Outline
Contents
1. Overview
General Description
Board Component Blocks
Block Diagram
Handling the Board
2. Board Components
Introduction
Board Overview
HSMC Connector (J1)
Santa Cruz Connectors (J3, J4, and J5)
USB On-The-Go Transceiver (U11)
MICTOR Connector (J2)
SD Card Interface (J7)
SMA Connector (J6)
I2C Serial EEPROM (U10)
Power Supply
Additional Information
Revision History
How to Contact Altera
Typographic Conventions
See also other documents in the category Altera Measuring instruments:
MAX 10 JTAG
(15 pages)
MAX 10 Power
(21 pages)
Unique Chip ID
(12 pages)
Remote Update IP Core
(43 pages)
Device-Specific Power Delivery Network
(28 pages)
Device-Specific Power Delivery Network
(32 pages)
Hybrid Memory Cube Controller
(69 pages)
ALTDQ_DQS IP
(117 pages)
MAX 10 Embedded Memory
(71 pages)
MAX 10 Embedded Multipliers
(37 pages)
MAX 10 Clocking and PLL
(86 pages)
MAX 10 FPGA
(26 pages)
MAX 10 FPGA
(56 pages)
USB-Blaster II
(22 pages)
GPIO
(22 pages)
LVDS SERDES
(27 pages)
User Flash Memory
(33 pages)
ALTDQ_DQS2
(100 pages)
Avalon Tri-State Conduit Components
(18 pages)
Cyclone V Avalon-MM
(166 pages)
Cyclone III FPGA Starter Kit
(36 pages)
Cyclone V Avalon-ST
(248 pages)
Stratix V Avalon-ST
(286 pages)
Stratix V Avalon-ST
(293 pages)
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP
(10 pages)
Arria 10 Avalon-ST
(275 pages)
Avalon Verification IP Suite
(224 pages)
Avalon Verification IP Suite
(178 pages)
FFT MegaCore Function
(50 pages)
DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP
(140 pages)
Floating-Point
(157 pages)
Integer Arithmetic IP
(157 pages)
Embedded Peripherals IP
(336 pages)
JESD204B IP
(158 pages)
Low Latency Ethernet 10G MAC
(109 pages)
LVDS SERDES Transmitter / Receiver
(72 pages)
Nios II Embedded Evaluation Kit Cyclone III Edition
(3 pages)
Nios II Embedded Evaluation Kit Cyclone III Edition
(80 pages)
IP Compiler for PCI Express
(372 pages)
Parallel Flash Loader IP
(57 pages)
Nios II C2H Compiler
(138 pages)
RAM-Based Shift Register
(26 pages)
RAM Initializer
(36 pages)
Phase-Locked Loop Reconfiguration IP Core
(51 pages)
DCFIFO
(28 pages)