HP XU700 - Manual (Page 40)

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2 System Board
Memory Controller Hub (82850)
MCH will scrub single bit errors by writing the corrected value back into
DRAM for all reads when hardware scrubbing is enabled. This, however does
not include reads launched in order to satisfy an AGP aperture transaction.
ECC can only be enabled when all RDRAM devices are populated in a system
that supports the extra two data bits used to store the ECC code.
Dual Rambus Bus
The Dual Rambus bus is comprised of 16 x 2 bits of data information, and
8 bits of Error Correcting Code (ECC). The bus is connected to the RIMM
memory slots and to the MCH chip supporting two Dual Rambus channels
(A and B).
Both channels run at 300 or 400 MHz supporting up to 32 rambus devices
per channel. The maximum available data bandwidth is 3.2 GB/s at 400 MHz.
The configuration of both primary rambus channels must be symmetrical –
the memory configuration on channel A must be identical to the memory
configuration on channel B. This means the memory must be installed in
identical pairs.