HP RX8620-32 - Manual (Page 17)

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I/O controller chips
The HP Integrity rx7620-16 and rx8620-32 Servers contain two master I/O controller chips located
on the PCI-X backplane. Each I/O controller contains 16 high-performance, 12-bit-wide links. These
links connect to 16 slave I/O controller chips supporting the PCI-X card slots and core I/O.
In both systems, two links—one from each master controller—are routed through the system backplane
and are dedicated to core I/O. The remaining 30 links are divided among the 16 133 MHz × 64-bit
PCI-X card slots, with each slot on a dedicated PCI-X bus. This one-card-per-bus architecture leads to
greater I/O performance, better error containment, and higher availability.
Each controller chip is also directly linked to a host cell board. This means that two cell boards,
located in cell slots 0 and 1, must be purchased in order to access all available I/O card slots. (With
one cell board, access to half of the available slots is enabled.)
PCI-X backplane
Figures 12 and 13 show detailed views of the HP Integrity rx7620-16 and rx8620-32 Server PCI-X
backplanes. The I/O slot implementations between the two servers are almost identical—the
difference is the use of one or two slots by the Integrity rx7620-16 Server core I/O. In both figures,
note that 14 of the 16 I/O card slots are supported by dual high-performance links. These dual-link
I/O slots provide a maximum of 1.06 GB/s of peak bandwidth for the slot. The remaining two I/O
slots are single links and provide a maximum of 530 MB/s of peak bandwidth. Aggregate I/O slot
bandwidth is 15.9 GB/s.
Every PCI-X slot in the HP Integrity rx7620-16 and rx8620-32 Servers is capable of running at
133 MHz × 64 bits. This means that every I/O slot will allow the industry’s highest-performing PCI-X
cards to run at their maximum design speed.