HP RX8620-32 - Manual (Page 13)

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Cell design details
Each cell board is a self-contained unit, with a symmetric multiprocessor (SMP), main memory, and all
necessary hardware.
• CPUs—up to four 1.6/1.5 GHz Intel Itanium 2 processors or four 1.1 GHz HP mx2 Dual-Processor
Modules (consisting of eight Intel Itanium 2 processors)
• Cell controller ASIC
• Memory controller (buffer) ASIC
• Main memory DIMMs (up to 16 DIMMs per cell board)
• Voltage regulator modules (VRMs)
• Data buses
The cell controller ASIC (CC) is at the heart of each cell board. The CC provides the communications
link between processors, memory, I/O, processor-dependent hardware (PDH), and adjacent cells.
The cell controller chip contains interface logic and maintains cache coherency throughout the system.
Adjacent to the cell controller ASIC are up to four Intel Itanium 2 processors or HP mx2 Dual-Processor
Modules and up to 64 GB of main memory. Each cell interfaces with adjacent cells and I/O
resources either directly or, in the case of the Integrity rx8620-32 Server, through the crossbar
backplane.
The primary function of the memory controller ASIC is to multiplex and de-multiplex data between the
cell controller ASIC and the SDRAM in the memory subsystem. When the cell controller ASIC issues a
read transaction to the memory interface command bus, the memory controller ASIC buffers the
DRAM read data and returns it as soon as possible. When the cell controller issues a write
transaction, the memory controller ASIC receives the write data from the cell controller ASIC and
forwards it to the DRAMs.
Note that only the data portion of the memory subsystem goes through the memory controller ASIC.
All address and control signals to the DIMMs are generated by the cell controller ASIC and sent
directly to the DIMM via the memory interface address bus.
The memory subsystem is a quad-ported implementation. It supports memory DRAM fault tolerance, in
which a discrete SDRAM chip can fail without compromising data integrity. The memory subsystem
provides 16 GB/s of peak bandwidth to the cell controller ASIC and reduces the overhead typically
associated with directory coherency.
Cell configurations
The Integrity rx7620-16 Server supports a minimum of one and a maximum of two cells. The Integrity
rx8620-32 Server supports a minimum of one and a maximum of four cells. When configured with
Intel Itanium 2 processors, each cell can be purchased with two or four active Intel Itanium 2
processors or HP mx2 Dual-Processor Modules. When configured with HP mx2 Dual-Processor
Modules, each cell can be purchased with one, two, three, or four active processor modules
(providing two, four, six, or eight total Intel Itanium 2 processors). The fully loaded Integrity rx7620-
16 Server will therefore contain eight Itanium 2 processors or eight HP mx2 Dual-Processor Modules
(16 CPUs). The fully loaded Integrity rx8620-32 Server will therefore contain 16 Itanium 2 processors
or 16 HP mx2 Dual-Processor Modules (32 CPUs). They may also be purchased in combination with
inactive Instant Capacity processors.
Both systems support traditional Intel Itanium 2 processors in two speeds: 1.6 GHz with 6 MB of cache
or 1.5 GHz with 4 MB of cache. They also support HP mx2 Dual-Processor Modules in one speed: 1.1
GHz with 4 MB of L3 cache and 32 MB of L4 cache. The ability to mix processor speeds within a
chassis is supported, but processors within a cell or partition must be the same speed. In addition, the
ability to mix CPU types (between traditional Intel Itanium 2 processors and HP mx2 Dual-Processor
Modules) is also supported, but processors within a cell or partition must be the same type.