Epson SED 1520 Series - Manual (Page 11)

SED1520 Series
2–2 EPSON
A
0
,CS
Display data latch circuit
LCD drive circuit
Common counter
Display start line register
Line counter
Line address decoder
Column address decoder
Column address counter
Column address register
Status
Command
decoder
Display
timing
generator
circuit
MPU interface
I/O buffer
Display data RAM
(2560-bit)
Low-address
register
Bus
holder
CL
FR
D
0
~D
7
(E,R/W)
COM
0
to COM
15
V
1
,V
2
,V
3
,V
4
,V
5
SEG
0
to SEG
60
RD,WR
V
DD
V
SS
RES
M/S
BLOCK DIAGRAM
An example of SED1520 * AA: