Grass Valley MPEG Upgrade - Manual (Page 31)

Audio Clock and Sharcnet Cabling
MPEG Board Upgrade Installation 21
Audio Clock and Sharcnet Cabling
This section explains how to connect Sharcnet and audio clock cables between
Audio Signal Processing Boards (ASPB) and video I/O boards. Each ASPB has
four Sharcnet connectors for embedded digital audio, two Sharcnet connectors for
interconnection with another ASPB, four audio record clock connectors and two
reference clock input connectors. Serial digital I/O boards have two Sharcnet
connectors for input and output of embedded audio, and two record clock output
connectors. Analog composite I/O boards only have two record clock output
connectors, as they do not support embedded audio.
General Sharcnet Rules
Serial digital I/O boards extract embedded audio, route it to the ASPB, and receive
audio output from the ASPB to be embedded in the serial digital stream.
Beginning with the ASPB in the lowest numbered slot, the fourth Sharcnet
connector from the rear panel is connected to the first Sharcnet connector (also
from the rear) on the serial digital I/O board in the lowest numbered slot. Next, the
sixth connector from the rear on the ASPB is connected to the second connector
on the serial digital I/O board.
If you have a second serial digital I/O board, the third connector on the ASPB is
connected to the first connector on the second serial digital I/O board; then, the
fifth to the second. See an example of Sharcnet cabling for one serial digital I/O
board in Figure 7, for two boards in Figure 8, and for four boards in Figure 9.
NOTE: The Sharcnet connectors on the MPEG boards are not used at this
time.
General Audio Clock Rules
On an ASPB, there is one audio record clock input connection for each bank of
four audio channels, so that there are four record clock input connectors for the
sixteen audio channels on an ASPB.The first input record clock connector, for the
first bank (channels 1 through 4), is the one closest to the rear of the chassis, and
the next three connectors follow the sequence for banks 2, 3, and 4. The remaining
two connectors are not used.