Grass Valley 8950DAC - Manual (Page 41)

8950DAC Instruction Manual 41
Functional Description
Functional Description
Refer to the block diagram in Figure 17 while reading the following func-
tional description.
Figure 17. 8950DAC Block Diagram
The 8950DAC converts SMPTE 259M (270 Mb/s D1 serial component
digital signal) to Y/B-Y/R-Y, or GBR analog video.
The major functional blocks are:
• Serial input and deserializers,
• Phase Lock Loop (PLL) 2 times clock generator,
• Digital to Analog converter (DAC),
• Output Low Pass Filters (LPF) and buffers,
• Delay line,
• Embedded processor, and
• Digital Signal Processing (DSP) Field Programmable Gate Array
(FPGA).
To Host
Serial input
Matrix select
Bypass control
DAC
DAC
DAC
DAC LPF
LPF
LPF
LPF
B
B
B
Comp. Sync
Y/G
B-Y/B
R-Y/R
Composite
Sync
Y/G
B-Y
R-Y
Deserializer Y/B-Y/R-Y Y/B-Y/R-Y
B
8 X
DAC OFFSET
GAIN Parallel
Interface
DSP FPGA
Timing
Analog Sync Gen.
4 Times Over-sampling
Filters
Color Space Converter
Delay
(3 line
max.)
54 MHz Osc.
and PLL
Embedded
Processor
User
Setup
Sw.
LEDs
0604_01