Grass Valley 8920DAC - Manual (Page 24)

18 8920DAC Instruction Manual
8920DAC AES/EBU to Analog Audio Converter
Control and Routing FPGA
The FPGA receives its programming and control information from the CPU
at power up. It also is able to receive mode commands from a four-bit
rotary switch. The FPGA receives an digital audio serial stream from the
receiver and sends its outputs to the output DAC. The FPGA also performs
the following functions:
■ Decodes and drives the front panel LEDs,
■ Passes clock and audio information to the DAC for analog decoding,
■ Enables the appropriate emphasis filter for both channels for the
received sample rate on the DAC, and
■ Enables a soft mute that ramps up/down in about 20 ms (depending on
sample rate).
CPU (Controller)
The primary purpose of the CPU is to provide remote monitoring capa-
bility for the 8920DAC. It receives information about:
■ Sample rate,
■ Emphasis,
■ Error,
■ Mode selection, and
■ Digital signal present
This information is passed through the frame controller to a remote moni-
toring location. A removable jumper is provided to allow disabling of
remote control.
Digital/Analog Converter (DAC), Filter, Gain, and Output Stages
The DAC consists of a single, stereo, 24-bit, 128x over-sampling DAC. The
outputs of the DACs are differential. They are received by a differential
receiver, which also serves as a Low Pass Filter. The signal then passes
through to the gain stage.
The output drivers provide precision signal balance and output common
mode rejection.