Verilink SCC 2130 (880-503282-001) Product Manual - Manual (Page 44)

Configuration
3-24 Verilink SCC 2130 User Manual
65 DIU 2140 Sets DTE timing option for all synchronous data ports to ST
66 DIU 2140 Sets DTE timing option for all synchronous data ports to ST
67 DIU 2140 Sets DTE timing option for all synchronous data ports to TT
68 DIU 2140 Sets RTS to normal operation, for synchronous data ports, data is
transmitted ONLY if the DTE asserts RTS, (ignored in Async) [default]
69 DIU 2140 Sets RTS to forced on (requires version 1.1 DIU 2140 firmware), data is
sent regardless of actual state of RTS from DTE: this behavior always
applies to async ports
80 SCC 2130
TAC 2130
DIU 2130
Set Data Port 1 to tail-circuit timing. Note that TAC 2130-T and TAC
2130-S modules do not support tail circuit timing, external timing or
TIU 2850 timing
81 SCC 2130
TAC 2130
DIU 2130
DSU canned configuration #1, assigns all 24 timeslots to data port #1
82 SCC 2130
TAC 2130
DIU 2130
DSU canned configuration #2, assigns timeslots 1-12 to data port #1
and timeslots 13-24 to data port #2 (data port #2 ignored by TAC/SCC
2130)
83 SCC 2130
TAC 2130
DIU 2130
DSU canned configuration #3, assigns timeslots 1-8 to data port #1
and timeslots 9-16 to data port #2 (data port #2 ignored by TAC/SCC
2130)
84 SCC 2130
TAC 2130
DIU 2130
DSU canned configuration #4, assigns timeslots 1-6 to data port #1
and timeslots 7-12 to data port #2 (data port #2 ignored by TAC/SCC
2130)
85 SCC 2130
TAC 2130
DIU 2130
DSU canned configuration #5, assigns timeslots 1-4 to data port #1
and timeslots 5-8 to data port #2 (data port #2 ignored by TAC/SCC
2130)
86 SCC 2130
TAC 2130
DIU 2130
DSU canned configuration #6, assigns timeslots 1-2 to data port #1
and timeslots 3-4 to data port #2 (data port #2 ignored by TAC/SCC
2130)
87 SCC 2130
TAC 2130
DIU 2130
DSU canned configuration #7, assigns timeslots 1-23 to data port #1
and timeslot 24 to data port #2 (data port #2 ignored by TAC/SCC
2130)
88 SCC 2130
TAC 2130
DIU 2130
DIU 2131
Set DTE port(s) clock to TT, data port samples Transmit Data during
negative going transition of clock received from DTE (on the pair
Terminal Timing in RS-422, SCTE in V.35 or XTC in RS-232)
89 SCC 2130
TAC 2130
DIU 2130
DIU 2131
Set DTE port(s) clock to inverted ST (ST) data port samples Transmit
Data lead during positive going transition of transmit clock signal
Code Applies to Description