Sundance SMT401 - Manual (Page 14)

Released Page 14 of 21 SMT401 PMC TIM Carrier User Guide
Document Name: SMT401 User Guide V1.2.doc Issue : 02 Rev.: 1.11
Enable Group
Bit 7 6 5 4 3 2 1 0
Name CLEAR
C40 INT
0 CLEAR
IBF INT
CLEAROB
E INT
C40 IE TBC IE IBF IE OBE IE
IBF IE
Input Buffer Full Interrupt Enable. Allows an interrupt to be generated when the host comm-port input
register is loaded with data from the C40.
OBE IE Output Buffer Empty Interrupt. Allows an interrupt to be generated when the host comm-port register has
transmitted its contents.
TBC IE Test Bus Controller Interrupt Enable. Interrupts from the Texas JTAG controller are enabled when set.
C40 IE C40 Interrupt Enable. Allows a programmed interrupt to be generated by the C40 when set.
CLEAR OBE
INT
Write a one to this bit to clear the interrupt resulting from a comm-port output event.
CLEAR IBF
INT
Write a one to this bit to clear the interrupt event resulting from comm-port input.
CLEAR C40
INT
Write a one to this bit to clear down the C40 INT event.
The JTAG controller which generates TBC INT must be cleared of all
interrupt sources in order to clear the interrupt.
4.3 PCI Master Operation
The first TIM position on the SMT401 PMC makes use of the global bus to
allow the C40 to read and write the entire PCI address space. Burst mode
and single transfers can be used to access the PCI address space.
Product Name: SMT401 Revision Date: 07 December 2004
Author: Mark I. Cartlidge (Updated by SM, added JTAG slave section) Original Date: 12 May 1999