Sundance SMT401 - Manual (Page 13)

Released Page 13 of 21 SMT401 PMC TIM Carrier User Guide
Document Name: SMT401 User Guide V1.2.doc Issue : 02 Rev.: 1.11
4.2.2 Status Register (Offset 14h)
The STATUS register can only be read.
Bit 31 30 29 28 27 26 25 24
Name
MODE 0 0 0 0 IIOF2 IIOF1 IIOF0
Bit 23 22 21 20 19 18 17 16
Name 0
0 CONFIG_L TBC RDY 0 MASTER IBF OBF
Bit 15 14 13 12 11 10 9 8
Name
0 0 0 0 0 0 0 INTA
Bit 7 6 5 4 3 2 1 0
Name
C40 INT TBC INT IBF INT OBE INT C40 IE TBC IE IBF IE OBE IE
OBE IE
Set if comm-port output buffer empty interrupts enabled.
IBF IE Set if comm-port input buffer full interrupts enabled
TBC IE Set if JTAG interrupts enabled
C40 IE Set if interrupt from TIM1 C40 enabled
OBE INT Set if comm-port output buffer becomes empty.
Cleared by writing a 1 to the corresponding bit in the interrupt control register.
IBF INT Set if comm-port input buffer receives a word.
Cleared by writing a 1 to the corresponding bit in the interrupt control register
TBC INT Set when the TBC asserts its interrupt.
Cleared by removing the source of the interrupt in the TBC.
C40 INT Set when the TIM1 C40 sets its host interrupt bit.
Cleared by writing a 1 to the corresponding bit in the interrupt control register.
INTA This is a logical OR of bits 7 to 4 in this register gated with the corresponding enable bit.
OBF Set when a word is loaded into the comm-port output register. Cleared when the word is transmitted
to the C40.
IBF Set when a word is received into the comm-port input register from the TIM1 C40.
MASTER When set, the comm-port interface token is owned by the SMT401 PMC bridge.
TBC RDY Reflects the current state of the TBC RDY pin. This bit is active high and therefore an inversion of
the TBC pin.
CONFIG_L Reflects the current state of the CONFIG signal from the TIM1 C40. Active low.
IIOF0,1,2 These reflect the state of the IIOF pins
MODE Reserved for Alphadata use.
4.2.3 Interrupt Control Register (Offset 18h)
This write-only register controls the generation of interrupts on the PCI bus.
Each interrupt source has an associated enable and clear flag. This register
can be written with the contents of bits 7:0 of the Status Register.
Product Name: SMT401 Revision Date: 07 December 2004
Author: Mark I. Cartlidge (Updated by SM, added JTAG slave section) Original Date: 12 May 1999