2 fpga clock structure, 3 fpga configuration – Sundance SMT166 User Manual
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4.2.2.2 FPGA Clock structure
SLB connectors show 4 LVDS clock lines (that’s 2 per SLB data bank). Xilinx Global
clock buffers can’t be used as there are simple not enough in the chip. Virtex6
FPGAs offer an alternative via the Regional Clock buffers. All clock lines coming
from the SLB connector are mapped to a Clock Capable pin, which allows connection
to BUFRs (Multi-Regional clock buffers). Each SLB has been assigned an FPGA pinout
made out of consecutive IO banks, which means that any SLB clock can be used to
latch in/out data lines anywhere from/to anywhere on the connector
Similarly, both parallel channels between the FPGAs have their clocks mapped on
multi-regional clock buffers.
Only the on-board clock is connected to Global Clock Buffer pads on the FPGAs.
System clocks required:
- 100-MHz general purpose clock (can be used for registers, RS232, etc),
- 200-MHz for the TEMAC interface (Coregen),
- 300-MHz for DDR3 idelay controller (DDR3 interface - Coregen),
- 400-MHz DDR3 clock (effectively clocks the DDR3 memory – defines the read
and write throughputs).
Alternatively, the clock coming out of one of the PCI Express cores can be used to
clock other interfaces and ensure a synchronisation in frequency and avoiding
crossing clock domains.
4.2.2.3 FPGA Configuration
Both FPGAs and CPLD can be programmed through the JTAG chain via a Xilinx
programming cable. FPGA configuration being volatile, the operation has to be done
again after each power off. The location of the Xilinx JTAG header is shown in
section 10.
Bitstreams can be stored into Flash Memory accessible from a host PC/unit via a
USB2.0 connection.
The SMT166 can be populated with FPGA ranging from the LX130T up to the
LX395T (all based on the same physical package).
Below is a table gathering sizes of bitstreams for each FPGA
FPGA
Bitstream size
Virtex6 LX130T
43.8 Mbits
Virtex6 LX195T
61.6 Mbits
Virtex6 LX240T
73.9 Mbits
Virtex6 LX365T
96.1Mbits
Virtex6 SX315T
104.5Mbits
Virtex6 SX475T
156.7Mbits
Figure 7 - FPGA Bitstream sizes.
Product Specification SMT166
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Last Edited: 17/06/2014 16:12:00