Measurement Computing PCM-QUAD02 - Manual (Page 7)

Chapter 1
Introducing the PCM-QUAD02
Overview: PCM-QUAD02 features
The PCM-QUAD02 is an 8-bit Type II PCMCIA card that provides inputs and decoding for up to two
incremental quadrature encoders. You can also use the PCM-QUAD02 as a high speed pulse counter for general
counting applications.
Quadrature encoders and the PCM-QUAD02
Incremental quadrature encoders are used to provide feedback signals from motors, that is, to count rotations
and convert the physical movement into a series of electrical signals. These signals are sent to the computer
which then decides whether or not to trigger signals that control the motor's movement and what those control
signals should be. The PCM-QUAD02 is the link between up to two incremental quadrature encoders and the
computer.
The PCM-QUAD02 card provides two channels for interfacing to incremental quadrature encoders. The heart
of this product is the LS7266, a 24-bit dual-axis quadrature counter IC from LSI Computer Systems, Inc. This
component contains the following:
ƒ 24-bit counters
ƒ Associated 24-bit preset and 24-bit output latch registers
ƒ Integrated digital filtering
ƒ 8-bit counter prescalers
ƒ programmable index functionality
ƒ programmable count modes, including non-quadrature modes
This functionality also enables the board to operate as a high speed pulse and general purpose counter,
cascadable to 48 bits. The 24-bit counter can count either in binary or BCD through the CMR register.
The Phase A, Phase B, and Index inputs are shipped configured for differential input, with termination resistor
locations populated.
ƒ If the resistor values are incorrect for your application, contact Measurement Computing Corporation to
have them replaced.
ƒ Attempting to open the PCM-QUAD02 voids the warranty.
This document provides diagrams showing how to connect single-ended encoders to the card. These signals,
after being routed through differential receivers, offer various paths to the LS7266 inputs. The inputs are routed
through the FPGA to allow various configurations for the following:
ƒ Individual encoder inputs for 2 channels.
ƒ Cascadable counters to allow non-quadrature counting up to 48-bits.
ƒ Routing of Index inputs to either the Load Counter/Load Latch input or the Reset Counter/Gate input with
quarter-cycle and half-cycle supported.
ƒ Routing the Compare or Carry/Borrow output signals to the interrupt circuit.
You may also generate interrupts from the two Index inputs, counter overflow/underflow, or count value match.
Two interrupt registers allow the software to enable/disable interrupts, mask individual interrupts, and read the
source of the interrupt.
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