Measurement Computing PCI-CTR10 - Manual (Page 8)

PCI-CTR10 User's Guide Introducing the PCI-CTR10
PCI-CTR10 block diagram
PCI-CTR10 functions are illustrated in the block diagram shown here.
PCI
CONTROLLER
BADR1
Interrupt
Boot
EEPROM
Control
Registers
Clock
Divider
Decode/Status
Int
Ctl
Bus
Timing
PCI-CTR10
Block Diagram
CLOCK SELECT
1/3.33/5 MHz
IRQ_A_Enable
IRQ_A_In
CONTROLLER FPGA and LOGIC
10 MHz
Oscillator
PCI BUS (5V, 32-BIT, 33 MHZ)
CLOCK SELECT
CONTROL
BUS
BADR2
Output
Port
Input
Port C
ont
ro
l Port_A OUTPUT(7:0)
Port_A INPUT(7:0)
Digital I/O
Counter 0
Co
nt
ro
l
AMD9513 (equivalent)
16 BIT COUNTERS
Counter 1
Counter 2
Counter 3
Counter 4
Input Clock0
Gate0
Output Clock0
Input Clock1
Gate1
Output Clock1
Input Clock2
Gate2
Output Clock2
Input Clock3
Gate3
Output Clock3
Input Clock4
Gate4
Output Clock4
1/3.33/5 MHz
IRQ_B_Enable
IRQ_B_In
Counter A
Output
Port
Input
Port Co
nt
ro
l Port_B OUTPUT(7:0)
Port_B INPUT(7:0)
Digital I/O
Counter 0
Co
nt
ro
l
AMD9513 (equivalent)
16 BIT COUNTERS
Counter 1
Counter 2
Counter 3
Counter 4
Input Clock0
Gate0
Output Clock0
Input Clock1
Gate1
Output Clock1
Input Clock2
Gate2
Output Clock2
Input Clock3
Gate3
Output Clock3
Input Clock4
Gate4
Output Clock4
1/3.33/5 MHz
Counter B
LOCAL BUS
CONTROL
BUS
Figure 1-1. PCI-CTR10 functional block diagram
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