Measurement Computing CIO-DAC04/12 - Manual (Page 15)

Counters Section
Configuration 82C54 device. 3 down-counters, 16 bits each, chained to form a 48-bit counter
Counter 0 - Internal Pacer - First divider
Source: 10 MHz oscillator
Gate: Internal PGATE (FPGA control signal)
Output: Chained to Counter 1 clock input
Counter 1 - Internal Pacer - Second divider
Source: Counter 0 output
Gate: Internal PGATE (FPGA control signal)
Output: Chained to Counter 2 clock input
Counter 2 - Internal Pacer - Third divider
Source: Counter 1 output
Gate: Internal PGATE (FPGA control signal)
Output: Pacer control logic
Clock input frequency 10 MHz max
High pulse width (clock input) 30 ns min
Low pulse width (clock input) 50 ns min
Gate width high 50 ns min
Gate width low 50 ns min
Input low voltage 0.8V max
Input high voltage 2.0V min
Output low voltage 0.4V max
Output high voltage 3.0V min
Environmental
Operating temperature range 0 to 70°C
Storage temperature range
−
40 to 100°C
Humidity 0 to 90% non-condensing
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