Measurement Computing CIO-DAC04/12 User Manual

Page 12

Base + 8 (Counter 0 Data)

Base + 9 (Counter 1 Data)

Base + 10 (Counter 2 Data)

Base + 11 (Counter Control)

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Definitions

DA11:0 "DAC04HS/12 - DAC Data bits: D11 = MSB, D0 = LSB (LEFT-JUSTIFIED)"

CHxH

DAC channel selection upper limit

CHxL

DAC channel selection lower limit
Examples:
"To sample channel 1: Set CH2L/CH1L to 0/1, CH2H/CH1H to 0/1"

"To sample channels 1 to 2: Set CH2L/CH1L to 0/1 (1), CH2H/CH1H to 1/0 (2)"

"To sample channels 0 to 3: Set CH2L/CH1L to 0/0 (0), CH2H/CH1H to 1/1 (3)"

FFE

"FIFO Empty: = 0 when empty, = 1 when not empty"

FFHF

"FIFO Half Full: = 0 when > half full, = 1 when < half full (512 samples)"

FFERR FIFO Error: = 1 if FIFO went empty during pacing (valid while pacer active)
INTST Interrupt Status: = 1 when FIFO half full
INTE

"Interrupt Enable: = 0 to enable interrupts, = 1 to disable"

SIMUL Simultaneous Update Mode: = 1 to enable simultaneous update of all 4 DAC's
START Start DAC conversions: = 1 to start conversions from pacer controlled

:= 0 to transfer 1 sample non-paced (direct mode)

DIN7:0

Digital Input byte

DOUT7:0

Digital Output byte

D7:0

Counter Data byte

INT2:0

Interrupt Select

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