Measurement Computing CIO-CTRxxHD - Manual (Page 11)

5.2 BASE +400 hex & BASE +401 hex
BASE + 400 controls the wait state for the board and the clock source and interrupt
level for 9513 #1 and 9513 #2
L0 L1 L2 CLK00 CLK01 CLK10 CLK11 WSEN
D0 D1 D2 D3 D4 D5 D6 D7
BASE +401 controls the clock source and interrupt level for 9513 #3 and 9513 #4
L0 L1 L2 CLK00 CLK01 CLK10 CLK11 X
D0 D1 D2 D3 D4 D5 D6 D7
Read - No read function for these registers.
Write - L0, L1, and L2 select IRQ as follows:
Table 5-2. IRQ Select Codes
7 1 1 1
6 0 1 1
5 1 0 1
4 0 0 1
3 1 1 0
2 0 1 0
N/A 1 0 0
N/A 0 0 0
IRQ L0 L1 L2
For BASE +400, CLK0# selects the clock cource for 9513 #1 (the chip designated
“U1”), CLK1# selects the clock source for 9513 #2 (the chip designated “U2”)
For BASE +401, CLK0# selects the clock cource for 9513 #3 (the chip designated
“U3” for the CIO-CTR20HD”), CLK1# selects the clock source for 9513 #4 (the chip
designated “U4” for the CIO-CTR20HD).
Table 5-3. Clock-Select Codes
N/A 1 1
External 0 1
5 MHz 1 0
1 MHz 0 0
CLOCK SOURCE CLK#0 CLK#1
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