Dell PowerEdge T610 - Manual (Page 30)

Dell
PowerEdge T610 Technical Guide 30
7 Memory
7.1 Overview
The PowerEdge T610 utilizes DDR3 memory, providing a high performance, high-speed memory
interface capable of low latency response and high throughput. The T610 supports Registered ECC
DDR3 DIMMs (RDIMM) or Unbuffered ECC DDR3 DIMMs (UDIMM).
Key features of the T610 memory system include:

Registered (RDIMM) and Unbuffered (UDIMM) DDR3 technology

Each channel carries 64 data and eight ECC bits

Support for up to 192 GB of RDIMM memory (twelve 16 GB RDIMMs)

Support for up to 24 GB of UDIMM memory (twelve 2 GB UDIMMs)

Support for 1066/1333 MHz single and dual rank DIMMs

Support for 1066 MHz quad rank DIMMs

Support for 1.35V low voltage (LV) DIMMs with 5600 series processors

Single DIMM configuration with DIMM at socket DIMM A1

Support ODT (On Die Termination)

Clock gating (CKE) to conserve power when DIMMs are not accessed

DIMMs will enter a low power self-refresh mode

I
2 C access to SPD EEPROM and thermal sensors

Single Bit Error Correction

SDDC (Single Device Data Correction, x4 or x8 devices)

Multi Bit Error Detection

Support for Closed Loop Thermal Management on RDIMMs and UDIMMs

Support for Advanced ECC mode

Support for Memory Optimized mode

Support for Memory Mirroring

Support for Memory Sparing with 5600 series processors
7.2 DIMMs Supported
The DDR3 memory interface consists of three channels with up to two RDIMMs or UDIMMs per channel
for single or dual rank and up to two RDIMMs per channel for quad rank. The interface uses 2 GB, 4
GB, 8 GB, or 16 GB RDIMMs. Also supported are 1 GB or 2 GB UDIMMs.
7.2.1 Memory Modes
The memory mode is dependent on how the memory is populated in the system, according to the
following configurations:

Three channels per processor populated identically
o Typically, the system will be set to run in Memory Optimized (Independent Channel)
mode in this configuration.
o This mode offers the most DIMM population flexibility and system memory capacity,
but offers the least number of RAS (reliability, availability, service) features.
o All three channels must be populated identically.

The first two channels per processor populated identically with the third channel unused
o Typically, two channels operate in Advanced ECC (Lockstep) mode with each other by
having the cache line split across both channels.
o This mode provides improved RAS features (SDDC support for x8-based memory).
o For memory mirroring, two channels operate as mirrors of each other (writes go to
both channels and reads alternate between the two channels).