Foxconn 45CSX - Manual (Page 32)

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The following 4 settings are valid only when the Configure DRAM Timing by SPD is set to
[Disabled].
► DRAM CAS# Latency
This item controls the CAS latency. The CAS Latency is the number of clock cycles that elapse
from the time the request for data is sent to the actual memory location until the data is transmit-
ted from the module.
► DRAM RAS# to CAS# Delay
This item allows you to select a delay time (in clock cycles) between the CAS and RAS strobe
signals.
► DRAM RAS# Precharge
This item allows you to select the DRAM RAS precharge time (in clock cycles).
► DRAM RAS# Activate to Precharge
This item allows you to set the precharge delay time (in clock cycles).