DFI CA900-B - Manual (Page 40)

40
3
BIOS Setup
CPU Configuration
This section is used to configure the CPU. It will also display the detected CPU
information.
For UP platforms,
leave it enabled.
For DP/MP servers,
it may use to tune
performance to the
specific application.
BIOS SETUP UTILITY
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.
← → Select Screen
↑↓ Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
Configure advanced CPU settings
Module Version:3F.15
Manufacturer : Intel
Celeron(R) Dual-Core CPU T3100 @ 1.90GHz
Frequency : 1.90GHz
FSB Speed : 800MHz
Cache L1 : 64KB
Cache L2 : 1024KB
Ratio Actual Value:9.5
Hardware Prefecher [Enabled]
Adjacent Cache Line Prefetch [Enabled]
Max CPUID Value Limit [Disabled]
Execute-Disable Bit Capability [Enabled]
Core Multi-Processing [Enabled]
Intel (R) Speedstep (tm) Tech [Enabled]
Advanced
Hardware Prefetcher
Enables or disables the Hardware Prefetcher feature.
Adjacent Cache Line Prefetch
Enables or disables the Adjacent Cache Line Prefetch feature.
Max CPUID Value Limit
Set this field to Disabled when using Windows XP. Set this field to Enabled
when using legacy operating systems so that the system will boot even when
it doesn’t support CPUs with extended CPUID function.
Execute Disable Bit Capability
When this field is set to Disabled, it will force the XD feature flag to always
return to 0.
Core Multi-processing
When this field is set to Disabled, it disables one execution core of each CPU
die.
Intel (R) SpeedStep(TM) Tech
Enables or disables GV3.