Aplex Technology ARCHMI-807 User Manual
Page 38
ARCHMI-8XX Series User Manual
37
17. CN1:
(1.25mm Pitch 2x20 Connector, DF13-40P), for 18/24-bit LVDS output connector,
fully supported by Parad PS8625(DP to LVDS), the interface features dual
channel 24-bit output. Low Voltage Differential Signaling, A high speed, low
power data transmission standard used for display connections to LCD panels.
Function
Signal Name
Pin#
Pin#
Signal Name
Function
LVDS
12V_S0
2
1
12V_S0
LVDS
BKLT_EN_OUT
4
3
BKLT_CTRL
Ground
6
5
Ground
LVDS_VDD5
8
7
LVDS_VDD5
LVDS_VDD3
10
9
LVDS_VDD3
Ground
12
11
Ground
LA_D0_P
14
13
LA_D0_N
LA_D1_P
16
15
LA_D1_N
LA_D2_P
18
17
LA_D2_N
LA_D3_P
20
19
LA_D3_N
LA_CLKP
22
21
LA_CLKN
LB_D0_P
24
23
LB_D0_N
LB_D1_P
26
25
LB_D1_N
LB_D2_P
28
27
LB_D2_N
LB_D3_P
30
29
LB_D3_N
LB_CLKP
32
31
LB_CLKN
Ground
34
33
Ground
USB3
(JP4 open)
USB3
(JP4 open)
USB3_P
36
35
USB3_N
5V_S5_USB
38
37
5V_S5_USB
Power LED
PWR_LED+
40
39
Ground
Power LED
18. JP4:
(2.0mm Pitch 2x2 wafer Pin Header), USB3(CN1) or Touch jumper setting.
JP4
Function
USB3 (CN1)
Touch (TCH1)
Close 3-4 (default)
-
Yes
Open 3-4 (option)
Yes
-
Open 1-2 (default)
-