Zilog Z80195 - Manual (Page 14)

Z80185/195 D EVELOPMENT K IT
U SER ' S M ANUAL
2-6 UM951800100
Z ILOG
SETTING UP THE HARDWARE (Continued)
ASCI0 DTE Pinning on J12
TXA0 drives TxD on J12.
RxD on J12 is received into RXA0.
/RTS0 drives RTS on J12
CTS on J12 is received onto J7-10 (/CTS0 on the schematic). It can be jumpered to the 185’s
/CTS0/RxS pin on J7-9, in which case this pin should be programmed for the /CTS0 function.
The signal on J14-12 (/DTR0 on the schematic) drives DTR on J12. It can be jumpered from the
185’s PIA13 pin on J14-11, or PIA12 on J14-13.
DSR on J12 is received onto J14-14 (/DSR0 on the schematic). It can be jumpered to the 185’s
PIA12 pin on J14-13, or PIA11 on J14-15.
DCD on J12 is received onto J7-8 (/DCD0I on the schematic). It can be jumpered to the 185’s
/DCD0/CKA1 pin on J7-7, in which case this pin should be programmed for the /DCD0 function. A
pull-up resistor is included on DCD from J12 so that it will appear asserted if the remote system doesn’t
drive DCD, as required by ASCI0.
RxC on J12 is received onto J7-4 (CK0I on the schematic). It can be jumpered to the 185’s CKA0/
CKS pin on J7-5, in which case this pin should be programmed for the CKA0 function, and CKA0
should be programmed as a 1X clock input.
The signal on J7-6 (CKOO on the schematic) drives TxC (DTE source) on J12. It can be jumpered
from the 185’s CKA0/CKS pin on J7-5, in which case this pin should be programmed for the CKA0
function and CKA0 should be programmed as a 1X clock output.
ASCI0 DCE Pinning on J13
The ASCI0 signals on the Z80185 are named appropriately for the DTE role, so the connections on
J13 are backward:
The ASCI0 TXA0 output drives RxD on J13.
The ASCI0 RXA0 input is taken from TxD on J13.
The ASCI0 RTS0 output drives CTS on J13.
The ASCI0 CTS0 input is taken from RTS on J13.
The signal on J14-12 (/DTR0 on the schematic) drives DSR on J13. It can be jumpered from the
185’s PIA13 pin on J14-11, or PIA12 on J14-13.