ADLINK PCI-9527 - Manual (Page 8)

viii Table of Contents
PCI-9527 ADLINK Technology Inc.
User’s Manual Copyright 2010
3.3 Analog Output Channel...................................................... 28
3.3.1 Analog Output Front-End Configuration ................... 28
3.3.2 Output Range and Data Format ............................... 29
3.3.3 DAC and Analog Output Filter .................................. 29
3.3.4 FIFO and DMA Transfer For Analog Output............. 30
3.4 Trigger Source and Trigger Mode...................................... 31
3.4.1 Trigger Sources ........................................................ 31
3.4.2 Trigger Mode ............................................................ 33
3.5 ADC and DAC Timing Control ........................................... 35
3.5.1 Timebase Architecture.............................................. 35
3.5.2 DDS Timing VS ADC/DAC Relationship................... 35
3.5.3 Timing Constraint When AI and
AO Enabled Simultaneously ..................................... 36
3.5.4 Filter Delay in ADC and DAC.................................... 37
4 Calibration ......................................................................... 39
4.1 Calibration Constant .......................................................... 39
4.2 Auto-Calibration ................................................................. 40
4.3 Offset Error Compensation During
AI Sampling Rate Change ....................................... 40