ADLINK PCI-7200 - Manual (Page 73)

C/C++ Libraries 61
bus master operation and can be a large number up to
64 million (2^26) bytes. Since PCI-7200 transfers are
always long words, this equals to 16 million long words
(2^24).
3. After the input sampling is started, the input data is
stored in the FIFO of PCI controller. Each bus mastering
data transfer continually tests if any data in the FIFO and
then blocks transfer, the system will continuously loop
until the conditions are satisfied again but will not exit the
block transfer cycle if the block count is not complete. If
there is momentarily no input data, the PCI-7200 will
relinquish the bus temporarily but returns immediately
when more input data appears. This operation continues
until the whole block is done.
4. This operation proceeds transparently until the PCI con-
troller transfer byte count is reached. All normal PCI bus
operations applied here, such as a receiver that cannot
accept the transfers, higher priority devices requesting
the PCI bus, etc. Remember that only one PCI initiator
can have bus mastering at any one time. However,
review the PCI priority and "fairness" rules. Also study
the effects of the Latency Timer. Additionaly, be aware
that the PCI priority strategy (round robin rotated, fixed
priority, custom, etc.) is unique to each host PC and is
explicitly not defined by the PCI standard. You must
determine this priority scheme for your own PC (or
replace it).
The interrupt request from the PCI controller can be optionally set
up to indicate that this loanword count is complete although this
can also be determined by polling the PCI controller.
@ Syntax
Visual C++ (Windows 95)
int W_7200_DI_DMA_Start (U8 mode, U32 count, U32
handle, Boolean wait_trg, U8 trg_pol,
Boolean clear_fifo, Boolean disable_di)