ADLINK PCI-7260 - Manual (Page 44)

34 Operation Theorem
COS detection circuit generates an interrupt request to PCI
controller.
COS Detection
The following timing is an example of COS operation. All of the
enabled DI channels’ signal level change will be detected to
generate the interrupt request.
While the interrupt request generates, the corresponding DI
data will also be latched into the COS latch register. In our COS
architecture, the DI data are sampled by a 8.25MHz clock. It
means the pulse width of the digital input have to last longer
than 122 ns, or the COS latch register won’t latch the correct
input data. The COS latch register will be erased after clearing
the interrupt request.
Figure 4-6: COS Timing