ADLINK PCI-7260 - Manual (Page 36)

26 Register Format
3.10 Interrupt / EMG_SHDN / WDT Status Register
When interrupt occurs, this register provides information for users
to recognize the interrupt status and the interrupt setup condition.
Address: BASE + 0x08
Attribute: Read
COS Int. Status (bit 0): COS interrupt Status
register
0: COS interrupt de-asserts
1: COS interrupt asserts
CH0 Int. Status (bit 1): Digital input channel 0
interrupt status
0: Ch0 interrupt de-asserts
1: Ch0 interrupt asserts
CH1 Int. Status (bit 2): Digital input channel 1
interrupt status
0: Ch1 interrupt de-asserts
1: Ch1 interrupt asserts
EMG SHDN Status (bit 3): Emergency Shutdown
status
0: EMG_SHDN de-asserts
1: EMG_SHDN asserts
CH1 Int. Status (bit 4): WDTimer interrupt status
0: WDTimer interrupt de-asserts
1: WDTimer interrupt asserts
7 6 5 4 3 2 1 0
--- --- ---
WDT Int
Status
EMG SHDN
Status
CH1 Int.
Status
CH0 Int.
Status
COS Int.
Status
15 14 13 12 11 10 9 8
--- --- ---
WDT
Int_EN
EMG EN
CH1
Int_EN
CH0
Int_EN
COS
Int_EN