ADLINK PCI-7260 - Manual (Page 34)

24 Register Format
3.9 Interrupt / WDT Control Register
There are three different interrupt modes in PCI-7260. In the first
mode, users enable the COS interrupt function to monitor the
enabled input channel’s status whenever the status changes from
0 to 1 or 1 to 0. In the second mode, users can select digital input
channel 0, channel 1 or both channels as the interrupt sources. In
this mode, interrupt only assertes when the DI status changes
from 0 to 1, i.e., rising edge. In the third mode, users can enable
WDTimer and let it count down. The interrupt assertes when
WDTimer is overflow. Because the three different modes share the
same interrupt signal in hardware, users are not allowed to enable
these tree modes at the same time.
After processing the interrupt request event, users have to clear
the interrupt request in order to handle another interrupt request.
To clear the interrupt request, write 1 to the corresponding bit.
Address: BASE + 0x08
Attribute: Write
COS CLR (bit 0): write 1 to clear the COS
interrupt.
1 : clear the COS interrupt
0 : no effect
CH0 CLR (bit 1): write 1 to clear DI channel 0
interrupt.
1 : clear DI channel 0 interrupt
0 : no effect
CH1 CLR (bit 2): write 1 to clear DI channel 1
interrupt.
1 : clear DI channel 1 interrupt
0 : no effect
WDT CLR (bit 7): write 1 to clear WDT interrupt.
1 : clear WDT interrupt
0 : no effect
COS Int_EN (bit 8): Write/Read
Change-of-State interrupt enable control
7 6 5 4 3 2 1 0
WDT CLR --- --- --- --- CH1 CLR CH0 CLR COS CLR
15 14 13 12 11 10 9 8
WDT Int_EN --- --- --- --- CH1 Int_EN CH0 Int_EN COS Int_EN