ADLINK PCI-7260 - Manual (Page 33)

Register Format 23
3.8 COS Latch Register
When COS occurs, the COS Latch register will also latch the DI
data. Once the user clear the interrupt request, the COS Latch
register will be cleared automatically. The COS function releases
the CPU from the burden of polling all of the input channels, and
enables the computer to handle higher I/O performance.
Address: BASE + 0x06
Attribute: Read
CL x: COS latch register of DI channel x, x = 0 ~
7
1: digital input voltage is in high level
0: digital input voltage is in low level
7 6 5 4 3 2 1 0
CL7 CL6 CL5 CL4 CL3 CL2 CL1 CL0
15 14 13 12 11 10 9 8
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