Appendix a: project structure and key filenames, Trademarks – Maxim Integrated MAXREFDES71 ZedBoard User Manual
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MAXREFDES71# ZedBoard Quick Start Guide
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8. Appendix A: Project Structure and Key Filenames
Top level folder contains:
• Numerous source and intermediate files (PlanAhead generated)
• top.ppr = main Xilinx PlanAhead project file.
• top.* = the Xilinx PlanAhead top level project folders
SDK Export Folder
• \MAXREFDESX = C Project Folder
• \src\MAXREFDESX.c = Main example program
• \src\maximDeviceSpecificUtilities.c = driver functions
• \src\menu.c = menu functions
• \src\utilities.c = generic system and FPGA helper functions
• \src\platform.c = low-level routines, Xilinx generated
• \MAXREFDESX_bsp_0 = Board support package
• \arm_system_hw_platform = Hardware platform specification
Driver folder for the AXI_MILLBRAE custom IP core
• \axi_millbrae_vX_XX_X\src\axi_millbrae.c = driver functions
• \axi_millbrae_vX_XX_X\src\axi_millbrae.h = driver header file
Pcore folder contains:
• The HDL source files for the AXI_MILLBRAE custom IP core
• \axi_millbrae_vX_XX_X\hdl\verilog\axi_millbrae.h = Top level design,
instantiates library components and user logic
• \axi_millbrae_v_X_XX_X\hdl\verilog\user_logic.v = User logic module that
implements the MAX11166 ADC and MAX5316 DAC SPI interfaces
9. Trademarks
ARM is a registered trademark of ARM Ltd.
Cortex is a trademark of ARM Ltd.
Eclipse is a trademark of Eclipse Foundation, Inc.
FMC is a trademark of Digilent Inc.
PlanAhead is a trademark of Xilinx, Inc.
WebPACK is a trademark of Xilinx, Inc.
Windows is a registered trademark and registered service mark and Windows XP is a
registered trademark of Microsoft Corporation.
Xilinx is a registered trademark and registered service mark of Xilinx, Inc.
ZedBoard is a trademark of ZedBoard.org.
Zynq is a registered trademark of Xilinx, Inc.