Kontron AT8902 - Manual (Page 51)

AT8902 Hardware Description
Page 3 - 17 AT8902 User Guide
3.1.8.5 Power Transients
The board provides continuous operation in the presence of transients shown in the following
table of the PICMG 3.0 standard:
Table 3-15: Power Transients
In case of a 0V transient the board is able to keep the board alive for 8ms. The necessary en-
ergy is buffered in a capacitor. The load time for the capacitor is 100s.
3.1.8.6 Optional Chassis to Logic Ground Connection
According to NEBS requirement R9-14 of GR-1089-CORE issue 3, the AT8902 provides a con-
nection between chassis and logic ground. It is made up of a screw that connects the PCB to
the bottom sheet.
If chassis and logic ground shall be isolated, the screw with its washer can be removed. It is
located near the jumper header J11 and is labelled "GND TO CHASSIS".
3.1.9 Reset
The reset chain is based on seven elements. The first element in the chain is the voltage supply
monitor, followed by the CPLD, FUM, IPMC, Payload voltage, PPC and Base Interface and fi-
nally the Fabric Interface.
The reset switch will perform a reset on the CPU when pressed for less than 1 second and a
complete board reset (including IPMI) when pressed for more than 2 seconds.
3.1.10 Jumpers
Five jumpers in the upper right corner allow debug settings (J11). The IPMI override jumpers
enable bypassing communication with the ShMC for bench operation. The JTAG jumpers con-
figure the boundary scan path. JTAG operation requires the use of an RTM.
Voltage Duration Comments Protected by
- 200 Volts 5 µs - 100 to - 200 Volts Frame or Shelf
- 100 Volts 10 µs - 75 to - 100 Volts Board
- 75 Volts 10 ms 10 Volts per ms-Rise or Fall Board
- 0 Volts 5 ms 50 Volts per ms-Fall
12.5 Volts per ms-Rise
Assumes prior voltage is above -44
VDC for Shelves, -43 VDC for
Boards
Board
Warning!
Operation with any of these jumpers set is not supported by the standard appli-
cation software.