Kontron CP372 - Manual (Page 57)

CP372 Configuration
ID 25780, Rev. 01 © 2002 Kontron Modular Computers GmbH Page 4 - 11
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P R E L I M I N A R Y
Table 4-2: DAC Common Control Register
Bit Map
BITS TYP. DEF. FUNCTION
31 R/W 0 Enable
30 - 8 R/W 00 reserved
7 - 6 R/W 00 RNG, BIP for DAC channel # 3
5 - 4 R/W 00 RNG, BIP for DAC channel # 2
3 - 2 R/W 00 RNG, BIP for DAC channel # 1
1 - 0 R/W 00 RNG, BIP for DAC channel # 0
Table 4-3: RNG, BIP Bits
RNG BIP INPUT RANGE
0 0 0 – 5 V
0 - 20 mA
1 0 0 – 10 V
0 1 ± 5 V
1 1 ± 10 V
Table 4-4: DAC Data Registers Bit Map
BITS TYPE DEFAULT FUNCTION
31 - 12 R 0 reserved
11 - 0 R 0 Data, 12 bit digit
4.3.3 Programming the Board Capability ROM
Besides correction data for gain and offset errors other board specific capabilities can be stored
in this dedicated onboard ROM. The purpose is to allow the software to configure itself accord-
ing to the hardware version (e.g. type, number of channels, insertion of components, input cir-
cuit, etc.).
The Board Capability ROM is implemented using a 4 KBit serial EEPROM of the type 93LC66
from Microchip.
The serial interface of the device has been realized in hardware resulting in a very simple reg-
ister based programming interface with command, control, and data registers. All protocol and
serial timing specifications are resolved by hardware.
Programming of the Board Capability ROM is undertaken as follows:
Tthe control word is written into the ROM Control Register including command opcode and in-
ternal address. Then optional data (in case of Write action) is written into the ROM Data Reg-
ister. Command execution is started by setting the Startbit in the ROM Command Register.
Then Ready/Busy must be polled in the ROM Status Register. After reaching Ready status, the
next command can be set up and data (in case of Read action) can be fetched from the ROM
Data Register.