Asus A8V-E - Manual (Page 85)

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4.4.2 4.4.2 4.4.2 4.4.2 4.4.2 Chipset Chipset Chipset Chipset Chipset
DRAM Configuration DRAM Configuration DRAM Configuration DRAM Configuration DRAM Configuration
The items in this sub-menu show the DRAM-related information
auto-detected by the BIOS.
F1:Help
↑↓
: Select Item -/+: Change Value F5: Setup Defaults
ESC: Exit
→←
: Select Menu Enter: Select Sub-menu F10: Save and Exit
Select Menu
Item Specific Help
Place an artificial
memory clock limit on
the system. Memory is
prevented from
running faster than
this frequency.
DRAM Configuration
Current DRAM Frequency 166 MHz
Max Memclock (MHz) [ Auto ]
CAS# latency (Tcl) [Auto]
RAS# to CAS# delay (Trcd) [Auto]
Min RAS# active time(Tras) [Auto]
Row precharge Time (Trp) [Auto]
Master ECC Enable [Enabled]
Phoenix-Award BIOS CMOS Setup Utility
Advanced
F1:Help
↑↓
: Select Item -/+: Change Value F5: Setup Defaults
ESC: Exit
→←
: Select Menu Enter: Select Sub-menu F10: Save and Exit
Select Menu
Item Specific Help
DRAM timing and
control
Chipset
DRAM Configuration
Upstream LDT Bus Width [16 bit]
Downstream LDT Bus Width [16 bit]
LDT Bus Frequency [Auto]
VLink Mode Selection [By Auto]
PEG Data Scrambling [Auto]
PE0-PE3 Data Scrambling [Enable]
Init Display First [PCI Slot
Chipset Vcore Adjustment [+1.6 V]
Phoenix-Award BIOS CMOS Setup Utility
Advanced
Current DRAM Frequency
Shows the Transfer mode. This item is not configurable.
Max Memclock (MHz) [Auto]
Sets the maximum operating memory clock.
Configuration options: [Auto] [DDR200] [DDR266] [DDR333]
[DDR400]