Cirrus Logic AN179 - Manual (Page 4)

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Copyright 2001 Cirrus Logic (All Rights Reserved) AN179REV2
EP72xx and EP73xx
CL2
M
DD[0:3] are the four data lines. When the LCD Controller writes out this port, it presents four pixels at a time using
these lines. Each data line is either HIGH or LOW. Thus each pixel value is either HIGH or LOW.
FRM is the frame sync signal. It toggles HIGH after all of the pixel data for a frame has been completely written out
the interface. It is used by the display to force it to reset its line (row) counter back to zero. Thus, the display will
start driving the next nibble of data to the first line of the display.
CL1 is the line strobe signal. It toggles HIGH after all of the pixel data for a line has been written out the interface.
CL2 is the pixel data clock. It is used by the display to clock in each nibble of pixel data. Its period is ¼ the actual
pixel rate. When CL1 toggles, CL2 stays LOW. Thus, CL2 LOW time is doubled when CL1 toggles at the end of
each line.
M is the AC Bias signal. This signal is used by the display to tell it when the drive voltage to the display should be
reversed. If used, it becomes active HIGH for a programmed quantity of CL2 cycles during each CL1 cycle. This is
done periodically to minimize any DC voltage bias that may build-up across the display. DC voltage build-up is
undesirable, since it can damage the display. The value for M is based upon the exact display being used.
Therefore, the value must be obtained from the display’s datasheet.
Example Color LCD MOdule Interface
The schematic diagram of Figure 1 depicts one example solution of interfacing the EP72xx LCD Controller to a
Sharp LM057QCTT03 ¼ VGA Color LCD module. This display has an 8-bit data interface. The sole purpose of this
logic is to convert the 4-bit interface into an 8-bit. It creates an 8-bit interface out of two 4-bit nibbles. This logic has
no affect on the programming of the LCD Controller registers. The LCD Controller will provide the same Refresh
Rate and pixel color depth.
The left side of the schematic has all the input signals from the LCD Controller. The right side has all the output
signals that connect directly to the display.
Since the data provided to the display is made up of two sets of data that is output from the EP72xx, the clock
supporting this 8-bit data word, must be half the rate as the original. This means that CL2 from the EP72xx must be
halved. This is accomplished by use of the D flip-flop configured to toggle its output every time its clock toggles
HIGH. By using EP72xx_CL2 as the input clock, the output toggles at ½ the clock rate, and thus becomes the
desired LCD_CL2.
EP72xx_CL1 is routed directly to the display. It is also used to reset the D flip-flop so that the signal LCD_CL2
starts off in the LOW State.
The ‘174 register is used to store the lower half of the 8-bit data word. When the upper nibble is available, both
nibbles are provided to the display together.