Cirrus Logic AN199 - Manual (Page 4)

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Copyright 2001 Cirrus Logic (All Rights Reserved) AN199Rev1
AN199
Programming the FIQHandler
MP3, AAC, WMA, etc., libraries decode left and right channel data which will both be stored at some designated
address by the memory buffer. This address will be passed to the FIQ Handler so that data can be moved into the
DAI left and right channel FIFOs.
• IMPORT the address of the buffers to the FIQ routine. This is the decompressed data to be used to fill the
FIFOs.
• If data exists, write 4 samples to each left then right channel in that order until both FIFOs are half- full. The
order here is important. Always start with the left channel and alternate with the right to make certain that
both FIFOs are filled properly.
• If no data exists in the buffers, write four samples of silence to the FIFOs alternating between the left then
right channels. Silence will consist of zeros. There is nothing decoded but the FIFOs are now half-full so the
program can return from the handler and begin processing data.
• Read four samples from the receive buffer regardless of whether there is music to be played or not. If
recording is not taking place at the time, discard the samples, otherwise store them into memory. This will
insure that the DAI FIFO information is in sync. Otherwise the data becomes out of sync and will sound
distorted.
• Clear overrun and underrun status bits in DAI status register in the same manner as mentioned above. This
will insure we avoid an endless loop.
Hardware Interface
Generating MCLK has changed from the EP7212 to the EP7312 microprocessors. This issue is taken separately
since the external hardware implementation is not described in detail in the EP73xx User’s Manual. Due to the
enhancement of the DAI interface for the EP7312, this has lead to additional chip resources required to insure all
signals are present at the external CODECs.
MCLK for the EP7212 is fed by an external oscillator (EXTCLK). That same signal is then passed to the external
CODEC. The clock signals created internally are SCLK and LRCLK. MCLK is simply an input. The EP7212 is
limited to 44.1 kHz sampled files, so the oscillator was fixed to 11.286 MHz or 256Fs. All music files, other than
those sampled at 44.1 kHz, are sample rate converted in software to 44.1 kHz, then sent to the external DAC.
MCLK for the EP7312 is routed differently. Instead of a fixed sample rate, the DAI now allows internal clock
adjustments to provide DAI clocking for all of the standard sample rates. To accommodate this change, MCLK is
now provided by means of the BUZ pin. This can be referred to as MCLK (BUZ) in the User’s Manual, or as
MCLKOUT.
MCLKIN (EXTCLK) is the MCLK signal pin on the DAI interface which can be programmed to receive either an
external clock source or the internal PLL clock as the clock source. The EP7312 64DAIFS register allows the user to
select what clock source will be used. This pin, as with the EP7212, is used as an input.
MCLK (BUZ) or MCLKOUT is also programmable by programming the 64DAIFS register. The signal, when
enabled, will come out on the BUZ pin. Since the BUZ pin is multiplexed with the annuciator, this resource is
dedicated either for that purpose, or for the DAI interface.
The diagram below shows the external hardware connections for MCLK. SCLK, LRCLK, SDTX, and SDRX are not
shown since these signals remain the same across the entire family of processors.