Cirrus Logic CDB61880 User Manual
Preliminary product information, Features, Description
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 2002
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CDB61880
Octal E1 Line Interface Evaluation Board
Features
z
Socketed CS61880 Octal Line Interface Unit
z
Binding post connectors for power and line
interface connections
z
Components supplied for all operational
modes E1 75
Ω and E1 120 Ω
z
Socketed termination circuitry for easy
testing
z
Connector for IEEE 1149.1 JTAG Boundary
Scan
z
LED Indicators for Loss of Signal (LOS) and
power
z
Supports Hardware, Serial, and Parallel Host
Modes
z
Easy-to-use evaluation software
z
On-board socketed reference clock oscillator
Description
The CS61880 evaluation board is used to demonstrate
the functions of a CS61880 Octal Line Interface Unit in
either E1 75
Ω or E1 120 Ω.
The evaluation board can be operated in either Hard-
ware mode or Host mode. In Hardware mode, switches
and bed stake headers are used to control the line con-
figuration and channel operations for all eight channels.
In Host mode (Serial or Parallel), the evaluation soft-
ware, switches, and bed stake headers are used to
control the line configuration and operating mode set-
tings for each channel.
In both Hardware and Host modes, the board may be
configured for E1 75
Ω or E1 120 Ω operating modes. In
both modes binding post connectors provide easy con-
nections between the line interface connections of the
CS61880 and any E1 analyzing equipment, which may
be used to evaluate the CS61880 device. Bed stake
headers allow easy access to each channel’s clock and
data I/O digital interface.
Eight LED indictors display the Loss of Signal (LOS)
conditions for each channel during Hardware and Host
modes. An LED indictor is used on the Interrupt pin to in-
dicate a change of state.
Note: Click on any
text
in blue to go to cross-references
ORDERING INFORMATION
CS61880-IQ
-40° to 85° C
144-pin LQFP
CDB61880
Evaluation Board
MAR ‘02
DS450DB1
Document Outline
- Features
- Description
- 1. CDB61880 Evaluation Board Layout
- 2. Board Component Descriptions
- 2.1 Power Connections
- 2.2 Master Clock Selection
- 2.3 Operating Mode Selection
- 2.4 Line Interface Connections
- 2.5 TXOE Selection
- 2.6 Clock Edge Selection
- 2.7 Jitter Attenuator Selection
- 2.8 Loopback Mode Selection
- 2.9 Line Length/Impedance Selection
- 2.10 Coder/Motorola/Intel Selection
- 2.11 G.772 Monitoring Address Selection
- 2.12 Mux/Non-Mux/BITS Clock Selection
- 2.13 Digital Signal Connections
- 2.14 LOS Indicators
- 2.15 JTAG Connection
- 2.16 Host Interface Connection
- 3. Host Setup Description
- 4. Host Software Interface
- 5. CS61880 Configuration Screens
- 6. Board Configurations
- 7. Evaluation Hints