Cirrus Logic CDB53L21 User Manual
Cdb53l21, Evaluation board for cs53l21, Features
Table of contents
Document Outline
- 1. System Overview
- 2. Software Mode Control
- 3. Hardware Mode Control
- 4. Performance Plots
- Figure 10. 0 dB FFT, Single-Speed Mode
- Figure 11. 0 dB FFT, Double-Speed Mode
- Figure 12. -60 dB FFT, Single-Speed Mode
- Figure 13. -60 dB FFT, Double-Speed Mode
- Figure 14. No Input FFT, Single-Speed Mode
- Figure 15. No Input FFT, Double-Speed Mode
- Figure 16. THD+N vs. Frequency, Single-Speed Mode
- Figure 17. THD+N vs. Frequency, Double-Speed Mode
- Figure 18. THD+N vs. Amplitude, Single-Speed Mode
- Figure 19. THD+N vs. Amplitude, Double-Speed Mode
- Figure 20. Fade-to-Noise Linearity, Single-Speed Mode
- Figure 21. Fade-to-Noise Linearity, Double-Speed Mode
- Figure 22. Frequency Response, Single-Speed Mode
- Figure 23. Frequency Response, Double-Speed Mode
- Figure 24. Channel Crosstalk, Single-Speed Mode
- Figure 25. Channel Crosstalk, Double-Speed Mode
- 5. System Connections and Jumpers
- 6. Block Diagram
- 7. Schematics
- Figure 27. CS53L21 (Part of Schematic Sheet 1)
- Figure 28. Analog I/O (Part of Schematic Sheet 1)
- Figure 29. S/PDIF I/O (Schematic Sheet 2)
- Figure 30. FPGA (Schematic Sheet 3)
- Figure 31. Level Shifters & I/O Stake Header (Schematic Sheet 4)
- Figure 32. Control Port I/O (Schematic Sheet 5)
- Figure 33. Power (Schematic Sheet 6)lm
- 8. Board Layout
- 9. Revision History