Cirrus Logic CS4397 - Manual (Page 14)

CS4397
14 DS333F1
SWITCHING CHARACTERISTICS - CONTROL PORT
(T
A
= 25 °C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, C
L
= 30 pF)
Notes: 12. t
spi
only needed before first falling edge of CS after RST rising edge. t
spi
= 0 at all other times.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For F
SCK
< 1 MHz
Parameter Symbol Min Max Unit
SPI Mode
CCLK Clock Frequency f
sclk
- 6 MHz
RST Rising Edge to CS Falling t
srs
500 - ns
CCLK Edge to CS Falling (Note 12) t
spi
500 - ns
CS High Time Between Transmissions t
csh
1.0 - µs
CS Falling to CCLK Edge t
css
20 - ns
CCLK Low Time t
scl
66 - ns
CCLK High Time t
sch
66 - ns
CDIN to CCLK Rising Setup Time t
dsu
40 - ns
CCLK Rising to DATA Hold Time (Note 13) t
dh
15 - ns
Rise Time of CCLK and CDIN (Note 14) t
r2
- 100 ns
Fall Time of CCLK and CDIN (Note 14) t
f2
- 100 ns
CCLK Falling to CDOUT valid t
ov
45 ns
t
r2
t f2
t dsu t dh
t sch t scl
CS
CCLK
t css
t csh
t spi
t srs RST
t
ov
CDIN
CDOUT
Figure 5. SPI Control Port Timing