Pin description, Pin name # pin description – Cirrus Logic CS4362 User Manual
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DS257F2
25
CS4362
5. PIN DESCRIPTION
Pin Name
#
Pin Description
VD
4
Digital Power (Input) - Positive power supply for the digital section. Refer to the Recom-
mended Operating Conditions for appropriate voltages.
GND
5
31
Ground (Input) - Ground reference. Should be connected to analog ground.
MCLK
6
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
illustrates several standard audio sample rates and the required master clock frequencies.
LRCK1
LRCK2
7
10
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the
serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
SDIN1
SDIN2
SDIN3
8
11
13
Serial Data Input (Input) - Input for two’s complement serial audio data.
SCLK1
SCLK2
9
12
Serial Clock (Input) - Serial clocks for the serial audio interface.
TST
14
44
45
Test - These pins need to be tied to analog ground.
RST
19
Reset (Input) - The device enters a low power mode and all internal registers are reset to their
default settings when low.
VA
32
Analog Power (Input) - Positive power supply for the analog section. Refer to the Recom-
mended Operating Conditions for appropriate voltages.
VLS
43
Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio
interface. Refer to the Recommended Operating Conditions for appropriate voltages.
VLC
18
Control Port Power (Input) - Determines the required signal level for the control port and
stand- alone configuration pins. Refer to the Recommended Operating Conditions for appropri-
ate voltages.
SDI
N
3
GND
AOUTB2-
AOUTA3+
AOUTB3-
AOUTB2+
VA
AOUTA3-
AOUTB3+
MUTEC2
MUTEC3
6
2
4
8
10
1
3
5
7
9
11
12
13 14 1 5 1 6 17 1 8 19 20 21 22 23 24
31
35
33
29
27
36
34
32
30
28
26
25
48 47 4 6 4 5 44 4 3 42 41 4 0 39 38 37
MCLK
DSDB1
VD
SDIN1
LRCK2
DSDA2
DSDA1
GND
SCLK1
SDIN2
SCLK2
LRCK1(DSD_EN)
M3
(D
S
D
_
S
C
L
K
)
DS
D
B
3
DS
D
A
3
TS
T
CS4362
TS
T
VLS
TS
T
M
2
(S
CL
/C
CL
K
)
M
1
(S
D
A
/C
DI
N)
VL
C
RST
FI
LT
+
VQ
MUT
E
C
6
MU
T
E
C
5
MUT
E
C
4
M0
(A
D
0
/C
S
)
AOUTA2+
AOUTA2-
AO
UT
B1+
AO
UT
B1-
AO
UTA
1
-
AO
UTA
1
+
DSDB2
MU
T
E
C
1