Cirrus Logic CS4340A - Manual (Page 7)

CS4340A
DS590F2 7
3.4 Digital Interface Format
The device will accept audio samples in several digital interface formats as illustrated in Table 5. The de-
sired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship between
LRCK, SCLK and SDIN, see Figures 2-5.
Sample Rate
(kHz)
MCLK (MHz)
256x 384x 512x 768x
32 8.1920 12.2880 16.3840 24.5760
44.1 11.2896 16.9344 22.5792 33.8688
48 12.2880 18.4320 24.5760 36.8640
Table 2. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
MCLK (MHz)
128x 192x 256x 384x
88.2 11.2896 16.9344 22.5792 33.8688
96 12.2880 18.4320 24.5760 36.8640
Table 3. Double-Speed Mode Standard Frequencies
Sample Rate
(kHz)
MCLK (MHz)
128x 192x
176.4 22.5792 33.8688
192 24.5760 36.8640
Table 4. Quad-Speed Mode Standard Frequencies
DIF1 DIF0 DESCRIPTION FORMAT FIGURE
0 0 I 2 S, up to 24-bit data 0 2
0 1 Left Justified, up to 24-bit data 1 3
1 0 Right Justified, 24-bit Data 2 4
1 1 Right Justified, 16-bit Data 3 5
Table 5. Digital Interface Format - DIF1 and DIF0
LR C K
S C L K
Left C ha nne l R ig h t C ha n nel
SDIN +3 +2 +1 +5 +4 M SB -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 LSB M SB LSB
Figure 2. CS4340A Format 0 - I
2
S up to 24-Bit Data