4 system dynamic range calculation, Converter and buffer noise analysis, Figure 3 . input buffer and adc block diagram – Cirrus Logic AN263 User Manual
Page 4: An263, Unweighted dr, 3 db

AN263
4
AN263REV1
2.4 System Dynamic Range Calculation
The un-weighted system dynamic range (in dB) can be calculated using the equation for the equivalent
system noise voltage. Conversion to A-weighting requires the addition of 3 dB to the un-weighted number.
Substituting and simplifying the equation yields;
A-weighted DR
sys
= unweighted DR
sys
+ 3 dB
3. Converter and Buffer Noise Analysis
One of the initial assumptions was that the buffer noise was negligible in relation to the converter noise.
Of the assumptions during the initial analysis, this has the greatest potential of being invalid. Though this
assumption proves to be acceptable for many applications and converter products, it becomes question-
able as converter dynamic range improves.
The calculation of the equivalent noise voltages for the ADC input buffers and DAC output buffers / filters
is beyond the scope of this paper. However, care needs to be taken to ensure that the converter and buffer
noise sources are referred to the appropriate system node. The converters themselves can be considered
unity gain devices and their noise can be referred to either the input or output of the converter. It’s gener-
ally best to refer the ADC buffer noise to the input of the ADC. In the case of the DAC, it is most convenient
to refer the noise of the DAC and buffer to the output of the buffer.
To illustrate the technique let's take a look at the combination of an input buffer and ADC, Figure 3. The
combined converter + buffer noise equation is shown below, assuming the buffer noise is referred to the
input of the ADC. The equivalent converter noise voltage can be calculated as previously shown.
Figure 3. Input Buffer and ADC Block Diagram
unweighted
DR
sys
20
V
fsdac
V
nsys
----------------
log
×
=
unweighted
DR
sys
10
–
10
DR
dac
10
----------------
⎝
⎠
⎛
⎞
–
10
DR
adc
10
----------------
⎝
⎠
⎛
⎞
–
+
log
×
=
Buffer
ADC
V
nT
V
nadc
2
V
nbuffer
2
+
=