Cirrus Logic AN263 - Manual (Page 2)

AN263
2 AN263REV1
of warning, the spectral noise content of digital-to-analog converters often do not retain this charac-
teristic at bandwidths well beyond 20 kHz when operated at 96 kHz or 192 kHz sample rates.
3) The noise contribution of the analog input and output stages are negligible. This assumption simplifies
the initial analysis but requires further investigation to ensure accuracy.
2. Combined ADC and DAC Dynamic Range Calculation
2.1 Converter Equivalent Noise Calculation
Dynamic Range (DR) is a specification that can be found in any ADC or DAC data sheet. This specification
is defined as the ratio of the RMS voltage of a full-scale analog input (V
fsadc
) or output (V
fsdac
) sine wave
to the RMS noise voltage of the converter over a 20 kHz bandwidth. DR is generally specified in dB and
the equation for dynamic range is shown below. Notice that there are three variables in this equation,
where the DR and V
fs
are common data sheet specifications. The equation can be easily rearranged to
allow the calculation of the equivalent RMS noise voltage (V
n
) of the converter.
However, adjustments to the data sheet Dynamic Range and full-scale input/output specifications are of-
ten required prior to the calculation.
1) Dynamic Range specifications are often A-weighted and the equivalent noise calculation requires the
use of un-weighted numbers. Fortunately, A-weighted specifications can easily be converted to an ap-
proximate unweighted specification. A conservative estimate can be determined by simply degrading
the A-weighted data sheet specification by 3 dB.
2) The full scale input or output voltage specifications in converter data sheets are commonly represent-
ed as either volts peak-to-peak, volts peak or RMS. The full scale input or output voltage must be con-
verted to a RMS value for this calculation to be valid.
2.2 Conversion System Gain
Another requirement is that the noise sources within the system must be referenced to the same system
node. Assume that the ADC and DAC system operates as a single block with analog input and analog
output. Due to the differences in the conversion processes and the corresponding differences in the ana-
log input voltage and the analog output voltage, the block has either gain or attenuation. The system must
be modeled to reflect this gain with the gain coefficient (K), as shown in Figure 2.
DR 20
V
fs
V
n
--------
⎝ ⎠
⎛ ⎞
log
×
=
V
n
V
fs
10
DR
20
--------- ⎝ ⎠
⎛ ⎞
------------------ =