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6 function configuration 1 (address 16h), 1 aux pll lock output configuration (auxlockcfg), 2 reference clock input divider (refclkdiv[1:0]) – Cirrus Logic CS2200-CP User Manual

Page 22: 7 function configuration 2 (address 17h), 1 enable pll clock output on unlock (clkoutunl), Warn, P 22, Aux pll lock output config, Cs2200-cp

6 function configuration 1 (address 16h), 1 aux pll lock output configuration (auxlockcfg), 2 reference clock input divider (refclkdiv[1:0]) | 7 function configuration 2 (address 17h), 1 enable pll clock output on unlock (clkoutunl), Warn, P 22, Aux pll lock output config, Cs2200-cp | Cirrus Logic CS2200-CP User Manual | Page 22 / 26 6 function configuration 1 (address 16h), 1 aux pll lock output configuration (auxlockcfg), 2 reference clock input divider (refclkdiv[1:0]) | 7 function configuration 2 (address 17h), 1 enable pll clock output on unlock (clkoutunl), Warn, P 22, Aux pll lock output config, Cs2200-cp | Cirrus Logic CS2200-CP User Manual | Page 22 / 26
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