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Miso (spi master in, slave out), Mosi (spi master out, slave in), Ssnot (spi slave select) – PNI MicroMag User Manual

Page 16: Drdy (data ready), 2 miso (spi master in, slave out), 3 mosi (spi master out, slave in), 4 ssnot (spi slave select), 5 drdy (data ready)

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PNI Sensor Corporation

DOC# 1015175 r01

MicroMag User Manual

– March 2010

Page 16 of 23

4.3.2 MISO (SPI Master In, Slave Out)

An SPI output that sends data from the MicroMag module to the master device.

Data is transferred most significant bit first. The MISO line is placed in a high

impedance state if the MicroMag is not selected by the master device (SSNOT = 1).

4.3.3 MOSI (SPI Master Out, Slave In)

An SPI input that provides data from the master device to the MicroMag module.

Data is transferred most significant bit first. Valid data must be presented at least

100 ns before the rising edge of SCLK, and remain valid for 100 ns after the rising

edge. New data may be presented to the MOSI pin after the falling edge of SCLK.

4.3.4 SSNOT (SPI Slave Select)

This signal sets the MicroMag module as the selected slave device on the SPI

bus. The SSNOT line must be LOW prior to data transfer in either direction, and

must stay LOW during the entire transfer. The SPI bus can be freed up (SSNOT line

set HIGH) for communication with another slave device while the MicroMag module

is taking a measurement or idle, but only after all communication between the

MicroMag and master device is finished. If the host system has no other slave

devices, the SSNOT line can be permanently grounded.

4.3.5 DRDY (Data Ready)

It is recommended the DRDY line be used to ensure data is clocked out of the

MicroMag only when it is available. DRDY is set low after a RESET. After a

command has been received and the data is ready, DRDY will be changed to high.

If it is determined the DRDY line cannot be used due to lack of I/O lines to the

host processor, then the times listed in Table 4-2 can be used to set open-loop wait

times. The values listed are the maximum delays from the end of the SCLK

command until the rise of the DRDY at each period select setting. The maximum

delay occurs when the sensor being sampled is in a zero field