IEI Integration IMBA-9454 v1.00 - Manual (Page 169)

IMBA-9454 Motherboard
Page 151
the manufacturer's code. The SPD enables the BIOS to read the spec sheet of the DIMMs
on boot-up and then adjust the memory timing parameters accordingly.
Disabled DRAM timing parameters can be manually set using
the DRAM sub-items
Enabled D EFAULT DRAM timing parameter are set according to the
DRAM Serial Presence Detect (SPD)
The Configure DRAM Timing by SPD option is disabled, the following configuration
options appear.
DRAM CAS# Latency [5]
DRAM RAS# to CAS# Delay [6 DRAM clocks]
DRAM RAS# Precharge [6 DRAM clocks]
DRAM RAS# Active to Precha [15 DRAM clocks]
DRAM CAS# Latency [5]
The DRAM CAS# Latency option refers to the Column Address Strobe (CAS) delay time.
To be able to change this configuration option the Configure DRAM Timing by SPD
configuration option must be set to “Disabled.” The following configuration options are
available.
3 nanoseconds
4 nanoseconds
5 nanoseconds D EFAULT
6 nanoseconds
DRAM RAS# to CAS# Delay [6 DRAM Clocks]
Use the DRAM RAS# to CAS# Delay option to specify the number of clock cycles must
elapse between sending a RAS (row address strobe) signal and the CAS (column address
strobe) signal. A pause is required between the RAS signal and the CAS signal to ensure
the memory is correctly addressed. To be able to change this configuration option the