IEI Integration PCIE-Q350 v1.00 - Manual (Page 12)

Page xii
PCIE-Q350 PICMG 1.3 CPU Card
6.7 C HIPSET ................................................................................................................. 154
6.7.1 NorthBridge Chipset Configuration .............................................................. 155
6.7.2 SouthBridge Configuration............................................................................ 158
6.8 E XIT ....................................................................................................................... 160
7 SOFTWARE DRIVERS ....................................................................................... 163
7.1 A VAILABLE S OFTWARE D RIVERS ............................................................................ 164
7.2 D RIVER CD A UTO - RUN .......................................................................................... 164
7.3 I NTEL ® C HIPSET D RIVER ....................................................................................... 166
7.4 I NTEL ® G RAPHICS M EDIA A CCELERATOR D RIVER ................................................ 170
7.5 I NTEL ® 82566 G IGABIT LAN C ONNECT D EVICE D RIVER ..................................... 175
7.6 I NTEL ® 82573 PCI E XPRESS G IGABIT E THERNET C ONTROLLER D RIVER ............. 182
7.7 R EALTEK HD A UDIO D RIVER (ALC883) I NSTALLATION ....................................... 191
7.7.1 BIOS Setup ..................................................................................................... 191
7.7.2 Driver Installation ......................................................................................... 191
7.8 I NTEL
®
M ATRIX S TORAGE M ANAGER D RIVER I NSTALLATION ............................... 197
7.9 I NTEL ® A CTIVE M ANAGEMENT T ECHNOLOGY D RIVER I NSTALLATION ................. 203
A BIOS OPTIONS.................................................................................................... 207
B DIO INTERFACE...................................................................................................211
B.1 DIO I NTERFACE I NTRODUCTION .......................................................................... 212
B.2 DIO C ONNECTOR P INOUTS ................................................................................. 212
B.3 A SSEMBLY L ANGUAGE S AMPLES ......................................................................... 213
B.3.1 Enable the DIO Input Function ................................................................ 213
B.3.2 Enable the DIO Output Function ............................................................. 213
C WATCHDOG TIMER............................................................................................ 215
D ADDRESS MAPPING ......................................................................................... 219
D.1 A DDRESS M AP ..................................................................................................... 220
D.2 1 ST MB M EMORY A DDRESS M AP ....................................................................... 220
D.3 IRQ M APPING T ABLE ........................................................................................... 221
D.4 DMA C HANNEL A SSIGNMENTS ............................................................................ 221
E INTEL
®
MATRIX STORAGE MANAGER ...................................................... 223
E.1 I NTRODUCTION ...................................................................................................... 224