SP / Silicon Power SP002GBSRU800S02 - Manual (Page 4)

DDR2 SODIMM
Product Specification
Pin Description
Symbol Type Description
A0–A13
Input
(SSTL_18)
Address inputs: Provide the row address for ACTIVE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one
device bank (A10 LOW, device bank selected by BA0–BA2) or all device banks
(A10 HIGH). The address inputs also provide the op-code during a LOAD MODE
command. A0–A12 (256MB) and A0–A13 (512MB, 1GB).
BA0–BA2
Input
(SSTL_18)
Bank address inputs: BA0–BA2 define to which device bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA0–BA2 define which mode
register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD
MODE command. BA0, BA1 (256MB, 512MB) and BA0–BA2 (1GB).
CK0, CK0#,
CK1, CK1#,
CK2, CK2#
Input
(SSTL_18)
Clock: CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and the negative
edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of
CK and CK#.
CKE0 ,CKE1
Input
(SSTL_18)
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW)
deactivates clocking circuitry on the DDR2 SDRAM.
ODT0, ODT1
Input
(SSTL_18)
On-die termination: ODT (registered HIGH) enables termination resistance
internal to the DDR2 SDRAM. When enabled, ODT is only applied to the following
pins: DQ, DQS, DQS#, and CB. The ODT input will be ignored if disabled via the
LOAD MODE command.
RAS#, CAS#,
WE# Input
(SSTL_18)
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
S0#, S1#
Input
(SSTL_18)
Chip select: S# enables (registered LOW) and disables (registered HIGH) the
command decoder.
SA0–SA2
Input
(SSTL_18)
Presence-detect address inputs: These pins are used to configure the
presence-detect devices.
SCL
Input
(SSTL_18)
Serial clock for presence-detect: SCL is used to synchronize the presence-detect
data transfer to and from the module.
SDA I/O
Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses
and data into and out of the presence-detect portion of the module.
DM0–DM7
I/O
(SSTL_18)
Data input mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH, along with that input data, during a write access. DM is
sampled on both edges of DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
DQ0–DQ63
I/O
(SSTL_18)
Data input/output: Bidirectional data bus.
DQS0–DQS7,
DQS0#–DQS7# I/O
(SSTL_18)
Data strobe: Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center-aligned with write data. DQS# is only
used when differential data strobe mode is enabled via the LOAD MODE command.
V
DD
/V
DDQ
Supply Power supply: 1.8V ±0.1V.
V
DDSPD
Supply Serial EEPROM positive power supply: +1.7V to +3.6V.
V
REF
Supply SSTL_18 reference voltage. (V
DD
/2)
V
SS
Supply Ground.
NC – No connect: These pins are not connected on the module.
Rev. 1.1 Aug. 2011 4