SP / Silicon Power SP004GBFRI800S01 - Manual

DDR2 Fully Buffered DIMM
Spec Sheet
1 Rev 1.0 Nov. 2010
Features
․240-pin, DDR2 Fully Buffered Dual In-line Memory Module (FBDIMM)
․High-speed, 1.5V differential, point-to-point link between the host controller and advanced
memory buffer (AMB)
․SMBus interface to AMB for configuration register access
․VDD = VDDQ = +1.8V,
․VDDSPD = +1.7V to +3.6V,
․VCC = 1.5V for AMB
․Channel fail over mode support
․Programmable CAS Latency: 3, 4, 5
․In-band and out-of-band command access
․MBIST and IBIST Test functions
․Automatic DDR2 SDRAM bus and channel calibration
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts