Impulse 7204 - Manual (Page 14)

Technical Description
Sealevel Systems ULTRA 485+2.PCI Page 11
Why use an ISP?
The answer to the polling inefficiency was the Interrupt Status Port (ISP). The
ISP is a read only 8-bit register that sets a corresponding bit when an interrupt is
pending. Port 1 interrupt line corresponds with Bit D0 of the status port, Port 2
with D1 etc. The use of this port means that the software designer now only has
to poll a single port to determine if an interrupt is pending.
The ISP is at Base+7 on each port (Example: Base = 280 Hex, Status Port = 287,
28F… etc.). The ULTRA 485+2.PCI will allow any one of the available
locations to be read to obtain the value in the status register. Both status ports on
the ULTRA 485+2.PCI are identical, so any one can be read.
Example: This indicates that Channel 2 has an interrupt pending.
Bit Position: 7 6 5 4 3 2 1 0
Value Read: 0 0 0 0 0 0 1 0