Asus AP120-E1 - Manual (Page 84)

4-20 Chapter 4: BIOS information
Configure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according
to the DRAM SPD (Serial Presence Detect). When disabled, you can
manually set the DRAM timing parameters through the following DRAM
sub-items.
Configuration options: [Disabled] [Enabled]
DRAM CAS# Latency [2.5 Clocks]
This item controls the latency between the SDRAM read command and
the time the data actually becomes available. Configuration options:
[2.0 Clocks] [2.5 Clocks] [3.0 Clocks]
DRAM RAS# Precharge [4 Clocks]
This item controls the idle clocks after issuing a precharge command to
the DDR SDRAM. Configuration options: [4 Clocks] [3 Clocks]
[2 Clocks]
DRAM RAS# to CAS# Delay [4 Clocks]
This item controls the latency between the DDR SDRAM active
command and the read/write command. Configuration options:
[4 Clocks] [3 Clocks] [2 Clocks]
DRAM Precharge Delay [8 Clocks]
Configuration options: [8 Clocks] [7 Clocks] [6 Clocks] [5 Clocks]
4.4.3 Chipset
The Chipset menu items allow you to change the advanced chipset
settings. Select an item then press Enter to display the sub-menu.
Advanced Chipset settings
WARNING: Setting wrong values in the sections below
may cause system to malfunction.
Configure DRAM TIming by SPD [Enabled]
Memory Acceleration Mode [Auto]
DRAM Idle Timer [Auto]
DRAM Refresh Rate [Auto]
Graphic Adapter Priority [PCI/AGP]
Graphics Aperture Size [ 64MB]
Spread Spectrum [Disabled]
ICH Delayed Transaction [Enabled]
MPS Revision [1.4]
Set DRAM timing
parameters according to
DRAM SPD or manually.