Asus CUSL2-C - Manual (Page 62)

ASUS CUSL2-C User’s Manual 62
4. BIOS SETUP
4. BIOS SETUP
Chip Configuration
SDRAM RAS to CAS Delay
This controls the latency between the SDRAM active command and
the read/write command.
SDRAM RAS Precharge Time
This controls the idle clocks after issuing a precharge command to the
SDRAM.
SDRAM Cycle Time (Tras, Trc) [6T, 8T]
This feature controls the number of SDRAM clocks used for SDRAM pa-
rameters Tras and Trc. Tras specifies the minimum clocks required be-
tween active command and precharge command. Trc specifies the mini-
mum clocks required between active command and re-active command.
Configuration options: [5T, 7T] [6T, 8T]
SDRAM Page Closing Policy [One Bank]
This feature controls that after a page miss whether the Graphics and
Memory Controller Hub (GMCH) will issue “precharge only the bank” or
“precharge all” command to a specific opened SDRAM bank. Configura-
tion options: [One Bank] [All Banks]
CPU Latency Timer [Enabled]
This controls the GMCH’s response to CPU deferrable cycles. Configura-
tion options: [Disabled] [Enabled]
Command Per Cycle [Enabled] (only for Intel 815E Chipset)
When onboard VGA is used, CPU can help to gain graphics performance
by increasing proper SDRAM cycles combinations. Configuration options:
[Enabled] [Disabled]
Onboard VGA [Enabled] (only for Intel 815E Chipset)
Leave on default setting if you want to use the onboard VGA. Select [Dis-
abled] if you want to use an add-on AGP or PCI VGA card. Configuration
options: [Disabled] [Enabled]
NOTE: The following 6 fields will only be displayed when the AGP Inline
Memory Module (AIMM) is used and Onboard VGA is set to [Enabled].
Display Cache [Enabled]
This field must be enabled to see the other Display Cache related con-
figuration fields. Configuration options: [Enabled] [Disabled]
Display Cache CAS Latency (DCCAS) [2T]
Configuration options: [2T] [3T]
Display Cache RAS to CAS Delay [Determined by DCCAS]
With the default setting [Determined by DCCAS], this field has the
same configuration as Display Cache CAS Latency (DCCAS). Con-
figuration options: [Determined by DCCAS] [2T]